1. Field of the Invention.
The present invention relates to a digital phase-locked loop clock extractor for bipolar signals.
More particularly, the clock extractor in accordance with the present invention comprises a circuit designed to allow taking from a PCM (pulse code modulation) input signal a clock signal phase locked to the input signal to allow sampling of the input signal latter with the clock signal without loss of information even in the presence of jitter (phase distortion) and frequency tolerance.
The function of clock signal extraction from a received data signal constituting the input signal has heretofore been done principally in the analog mode and recently also in the digital mode both with discrete and integrated circuit components.
The known prior art analog circuitry uses a tuned circuit or a frequency-controlled oscillator. Maintenance of an appropriate phase between the input signal and the clock signal takes place continuously and the clock signal extracted does not display phase jumps. These prior art circuits have been developed by some manufacturers of integrated circuits and can be implemented as well with discrete components. They display, however, criticality of operation, the need for calibration and generally poor reliability.
Clock extractors implemented digitally do not suffer from the aforementioned drawbacks. In order to meet the CCITT (International Telegraph and Telephone Consulative Committee) recommendations relative to jitter of the input data signal such known circuits produce a single considerable phase jump of the extracted clock. Such a phase jump appears even with low jitter at the input to compensate for the inevitable frequency differences between the line clock and the local clock.
In view of the aforementioned state of the art, the object of the present invention is to provide a clock signal extractor of the digital type which enables having in normal operating conditions a low phase jump capable of compensating for the frequency difference between the local clock and the line clock in the presence of low input jitter and at the same time in the presence of high jitter, permits sampling of the data signal received without loss of information, while producing a higher instantaneous phase correction of the generated clock signal.